The Addressing Modes - Reference - Programming the 65816 Including the 6502, 65C02, and 65802 (1986)

Programming the 65816 Including the 6502, 65C02, and 65802 (1986)

Part V. Reference

17. The Addressing Modes

There are fourteen addressing modes available to the 6502, all of those plus two more on the 65C02, and another nine categories available on the 65802 and 65816. Each mode allows the location of the data being referenced by a given instruction to be specified in a different manner. The availability of many different addressing modes on the 65x processors is one key to their power.

The data found in operand bytes of an instruction is only one part of the effective address specification; the addressing modes, expressed using the correct address-mode syntax in the operand field of an assembly-language statement, cause the assembler to choose from among the instruction's possible opcodes to one specific to the addressing mode. Not all addressing modes are available for all instructions; but there is one unique opcode for each combination of addressing mode and operation.

The addressing mode is the determinant of the effective address for an operation—the memory address that the instruction will access for data or to transfer control within the program. For a few of the 65x addressing modes, the effective address is provided in the operand field of the instruction. But for most of them, formation of the effective address involves an address calculation, that is, the addition of two or more values. The addressing mode used with a given instruction indicates where these values are to come from and how they are to be added together to form the effective address. This effective address calculation has as many forms as there are addressing modes.

An important aspect of effective address calculation on the 65802 and 65816, to be considered in addition to the addressing modes themselves, is the state of the x index-register select flag and, to a lesser extent, the m memory/accumulator select flag, both in the status register. In a sense, the x flag, for example, extends the addressing mode specification part of an instruction, which uses an indexed addressing mode, by determining whether or not an eight-bit or sixteen-bit index register is to be used. For every one of the indexed addressing modes, there are two similar methods of forming an effective address, depending on the setting of the index-register select flag. Pay special attention to the status and effects of the select flags.

In the following pages are graphic and written presentations of each of the addressing modes, illustrating the effective address formation, complete with a listing of the processors on which, and the instructions to which, each addressing mode is available. A sample of the assembler syntax used to invoke each one is included as well.

The descriptions are the complete set available on the 65816. The differences between the four processors, with their various modes, are graphically noted whenever possible.

The 65816's native mode features index registers and an accumulator which may be either eight bits or sixteen, depending on the settings of two mode select flags (x sets the index registers to eight or sixteen bits; m sets the accumulator and memory to eight or sixteen).

The 65802's native mode differs in that, while the bank registers are part of effective address formation, bank values are not propagated to the bus, so long addressing modes have no bank effect. The bank accessed is always bank zero, so there is, essentially, no bank portion to the effective address generated.

The 6502 emulation mode on the 65802 and 65816 processors (e = 1) differs in that the stack pointer's high byte is always $01; direct page indexed addressing always wraps around to remain in the direct page rather than crossing over into the next page (so the high direct page byte remains the high byte of all direct page addresses formed). The exception to this is that zero page stack wrapping is only enforced for 6502 and 65C02 instructions, and only when DP = 0 in the case of page zero wrapping. New opcodes will cause effective addresses to be generatedoutside of the zero page or the emulation mode stack page if an effective address calculation overflows the low byte.

Additionally, the index registers and the A accumulator are limited to eight bits. (There remains, however, a hidden eight-bit B accumulator, as well as a 16-bit C accumulator which is the concatenation of B and A but which is generally not accessible except to special instructions.)

The 65C02 and 6502 differ from 6502 emulation in that there are no bank registers whatsoever; direct page addressing is, instead, zero page addressing ($0000 is the zero page base to which offsets and, sometimes, index values are added; there is no direct page register); and there is no hidden B accumulator nor concatenated C accumulator.

The symbols in Table 17.1 are used to describe the kinds of operands that are used with the various addressing modes.

Figures 17.1 through 17.4 repeat the illustrations of the programming models for the four possible processor configurations: 6502/65C02, 65802 native mode, 65816 native mode, and 65816 emulation mode. The programming model for the native mode 65816 is used in the addressing mode figures that follow; for different processors or modes, compare the addressing mode figure with the processor-mode programming model for clarification of the operation of the addressing mode for that model.

Table 17.1. Operand Symbols.

Figure 17.1. 6502/65C02 Programming Model.

Figure 17.2. 65802 Native Mode Programming Model.

Figure 17.3. 65816 Native Mode Programming Model.

Figure 17.4. 65816 Emulation Mode Programming Model.

Absolute Addressing

Effective Address:

Bank:

Data Bank Register (DBR) if locating data; Program Bank Register (PBR) if transferring control.

High:

Second operand byte.

Low:

First operand byte.

Absolute Indexed, X Addressing

Effective Address: The Data Bank Register is concatenated with the 16-bit Operand: the 24-bit result is added to X (16 bits if 65802/65816 native mode, x = 0; else 8).

Absolute Indexed, Y Addressing

Effective Address: The Data Bank Register is concatenated to the 16-bit Operand: the 24-bit result is added to Y (16 bits if 65802/65816 native mode, x = 0; else 8).

Absolute Indexed Indirect Addressing

Effective Address:

Bank:

Program Bank Register (PBR).

High/Low:

The Indirect Address.

Indirect Address:

Located in the Program Bank at the sum of the Operand double byte and X (16 bits if 65802/65816 native mode, x = 0 ; else 8 bits).

Absolute Indirect Addressing

Effective Address:

Bank:

Program Bank Register (PBR).

High/Low:

The Indirect Address.

Indirect Address:

Located in Bank Zero, at the Operand double byte.

Absolute Indirect Long Addressing

Effective Address:

Bank/High/Low:

The 24-bit Indirect Address.

Indirect Address:

Located in Bank Zero, at the Operand double byte.

Absolute Long Addressing

Effective Address:

Bank:

Third operand byte.

High:

Second operand byte.

Low:

First operand byte.

Absolute Long Indexed, X Addressing

Effective Address: The 24-bit Operand is added to X (16 bits if 65802/65816 native mode, x = 0; else 8 bits)

Accumulator Addressing

8-Bit Data (all processors): Data: Byte in accumulator A.

16-Bit Data (65802/65816, native mode. 16-bit accumulator (m = 0):

Data High: High byte in accumulator A.
Data Low: Low byte in accumulator A.

Block Move Addressing

Source Effective Address:

Bank:

Second operand byte.

High Low:

The 16-bit value in X; if X is only 8 bits (mode flag x= 1), the high byte is 0.

Destination Effective Address:

Bank:

First operand byte.

High Low:

The 16-bit value in Y; if Y is only 8 bits (mode flag x = l) , the high byte is 0.

Count:

Number of bytes to be moved: 16-bit value in Accumulator C plus 1.

Direct Page Addressing

Effective Address:

Bank:

Zero

High/Low:

Direct Page Register plus Operand byte.

Direct Page Indexed, X Addressing

Effective Address:

Bank:

Zero

High/Low:

Direct Page Register plus Operand byte plus X (16 bits if 65802/65816 native mode, x = 0; else 8 bits).

Direct Page Indexed, Y Addressing

Effective Address:

Bank:

Zero

High/Low:

Direct Page Register plus Operand byte plus Y (16 bits if 65802/65816 native mode, x = 0; else 8 bits).

Direct Page Indexed Indirect, X Addressing

Effective Address:

Bank:

Data bank register

High/Low:

The indirect address

Indirect Address:

Located in the direct page at the sum of the direct page register, the operand byte, and X (16 bits if 65802/65816 native mode, x = 0; else 8), in bank 0.

Direct Page Indirect Addressing

Effective Address:

Bank:

Data Bank Register (DBR)

High/Low:

The 16-bit Indirect Address

Indirect Address:

The Operand byte plus the Direct Page Register, in Bank Zero

Direct Page Indirect Long Addressing

Effective Address:

Bank/High/Low:

The 24-bit Indirect Address

Indirect Address:

The Operand byte plus the Direct Page Register, in Bank Zero

Direct Page Indirect Indexed, Y Addressing

Effective Address:

Found by concatenating the data bank to the double-byte indirect address, then adding Y (16 bits if 65802/65816 native mode, x = 0; else 8).

Indirect Address:

Located in the Direct Page at the sum of the direct page register and the operand byte, in bank zero.

Direct Page Indirect Long Indexed, Y Addressing

Effective Address:

Found by adding to the triple-byte indirect address Y (16 bits if 65802/65816 native mode, x = 0; else 8 bits).

Indirect Address:

Located in the Direct Page at the sum of the direct page register and the operand byte in bank zero.

Immediate Addressing

8-Bit Data (all processors): Data Operand byte

16-Bit Data (65802/65816, native mode, applicable mode flag m or x = 0):

Data High:

Second operand byte.

Data Low:

First operand byte.

Implied Addressing

Type 1: Mnemonic specifies register(s) to be operated on

Type 2: Mnemonic specifies flag bit(s) to be operated on

Type 3: Mnemonic specifies operation; no data involved

Program Counter Relative Addressing

Effective Address:

Bank:

Program Bank Register (PBR).

High/Low:

The Operand byte, a two's complement signed value, is sign-extended to 16 bits, then added to the Program Counter (its value is the address of the opcode following this one).

Program Counter Relative Long Addressing’

Effective Address:

Bank:

Program Bank Register (PBR).

High/Low:

The Operand double byte, a two's complement signed value, is added to the Program Counter (its value is the address of the opcode following this one).

Stack (Absolute) Addressing

Source of data to be pushed: The 16-bit operand, which can be either an absolute address or immediate data.

Destination effective address: Provided by Stack Pointer.

Stack (Direct Page Indirect) Addressing

Source of data to be pushed: The 16-bit indirect address (or double-byte data) located at the sum of the Operand byte plus the Direct Page Register, in Bank Zero.

Destination effective address: Provided by Stack Pointer.

Stack (Interrupt) Addressing

Effective Address: After pushing the Program Bank (65802/816 native mode only), followed by the Program Counter and the Status Register, the Effective Address is loaded into the Program Counter and Program Bank Register, transferring control there.

Bank:

Zero

High/Low:

The contents of the instruction- and processor-specific interrupt vector.

Data: Source: Program Bank, Program Counter and Status Register.

Destination Effective Address: Provided by Stack Pointer.

Stack (Program Counter Relative) Addressing

Source of data to be pushed: The 16-bit sum of the 16-bit Operand plus the 16-bit Program Counter. (Note that the 16-bit Operand which is added is the object code operand; the operand used in the instruction's syntax required by most assemblers is a label which is converted to the object operand.)

Destination Effective Address: Provided by Stack Pointer.

Stack (Pull) Addressing

Source Effective Address: Provided by Stack Pointer.

Destination of data to be pulled: Register specified by the opcode.

The Stack Pointer (S) is incremented, specifying the location from which an 8-bit register—or the low byte of a 16-bit register—will be loaded. If the register is 16 bits, the Stack Pointer will be incremented a second time, and the register's high byte will be loaded from this second new Stack Pointer location.

Stack (Push) Addressing

Source of data to be pushed: Register specified by the opcode.

Destination Effective Address: Provided by Stack Pointer.

The Stack Pointer (S) specifies the location to which an 8-bit register—or the high byte of a 16-bit register—will be stored. The low byte of a 16-bit register will be stored to the Stack Pointer location minus one. After storage of an 8-bit register, S is decremented by 1; after a 16-bit register, S is decremented by 2.

Stack (RTI) Addressing

Source Effective Address: Provided by Stack Pointer.

Destination of values to be pulled: First the Status Register, then the Program Counter is pulled, followed (65802/65816 native mode only) by the Program Bank.

Control is transferred to the new Program Counter (and Program Bank) value(s).

Stack (RTL) Addressing

Source Effective Address: Provided by Stack Pointer.

Destination of values to be pulled: First the Program Counter is pulled and incremented by one. Then the Program Bank is pulled.

Control is transferred to the new Program Counter and Program Bank values.

Stack (RTS) Addressing

Source Effective Address: Provided by Stack Pointer.

Destination of values to be pulled: The Program Counter is pulled and incremented by one. The Program Bank remains unchanged.

Control is transferred to the new Program Counter value.

Stack Relative Addressing

Effective Address:

Bank:

Zero

High:Low:

The 16-bit sum of the 8-bit Operand and the 16-bit Stack Pointer.

Stack Relative Indirected Indexed, Y Addressing

Effective Address: The Data Bank Register is concatenated to the Indirect Address: the 24-bit result is added to Y (16 bits if 65802/65816 native mode, x = 0; else 8 bits).
Indirect Address: Located at the 16-bit sum of the 8-bit Operand and the 16-bit Stack Pointer.